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-- Company: 
-- Engineer: 
-- 
-- Create Date:    17:12:02 10/08/2013 
-- Design Name: 
-- Module Name:    cla_8bit - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity cla_8bit is
    Port ( a	: in	STD_LOGIC_VECTOR (7 downto 0);
			  b	: in	STD_LOGIC_VECTOR (7 downto 0);
			  cin : in  STD_LOGIC;
           cout : out  STD_LOGIC;
           sum : out  STD_LOGIC_VECTOR (7 downto 0));
end cla_8bit;

architecture Behavioral of cla_8bit is
component gp_blk
    Port ( a : in  STD_LOGIC;
           b : in  STD_LOGIC;
           g : out  STD_LOGIC;
           p : out  STD_LOGIC);
end component;

signal g,p: std_logic_vector (7 downto 0);
signal c1, c2, c3, c4, c5, c6, c7, c8: std_logic;

begin

gp0: gp_blk port map (a(0), b(0), g(0), p(0));
gp1: gp_blk port map (a(1), b(1), g(1), p(1));
gp2: gp_blk port map (a(2), b(2), g(2), p(2));
gp3: gp_blk port map (a(3), b(3), g(3), p(3));
gp4: gp_blk port map (a(4), b(4), g(4), p(4));
gp5: gp_blk port map (a(5), b(5), g(5), p(5));
gp6: gp_blk port map (a(6), b(6), g(6), p(6));
gp7: gp_blk port map (a(7), b(7), g(7), p(7));

c1 <= g(0) or (p(0) and cin);
c2 <= g(1) or (p(1) and g(0)) or (p(1) and p(0) and cin);
c3 <= g(2) or (p(2) and g(1)) or (p(2) and p(1) and g(0)) or (p(2) and p(1) and p(0) and cin);
c4 <= g(3) or (p(3) and g(2)) or (p(3) and p(2) and g(1)) or (p(3) and p(2) and p(1) and g(0))
		or (p(3) and p(2) and p(1) and p(0) and cin);
c5 <= g(4) or (p(4) and g(3)) or (p(4) and p(3) and g(2)) or (p(4) and p(3) and p(2) and g(1))
		or (p(4) and p(3) and p(2) and p(1) and g(0)) or (p(4) and p(3) and p(2) and p(1) and p(0) and cin);
c6 <= g(5) or (p(5) and g(4)) or (p(5) and p(4) and g(3)) or (p(5) and p(4) and p(3) and g(2))
		or (p(5) and p(4) and p(3) and p(2) and g(1)) or (p(5) and p(4) and p(3) and p(2) and p(1) and g(0))
		or (p(5) and p(4) and p(3) and p(2) and p(1) and p(0) and cin);
c7 <= g(6) or (p(6) and g(5)) or (p(6) and p(5) and g(4)) or (p(6) and p(5) and p(4) and g(3))
		or (p(6) and p(5) and p(4) and p(3) and g(2)) or (p(6) and p(5) and p(4) and p(3) and p(2) and g(1))
		or (p(6) and p(5) and p(4) and p(3) and p(2) and p(1) and g(0)) or (p(6) and p(5) and p(4) and p(3)
		and p(2) and p(1) and p(0) and cin);
c8 <= g(7) or (p(7) and g(6)) or (p(7) and p(6) and g(5)) or (p(7) and p(6) and p(5) and g(4))
		or (p(7) and p(6) and p(5) and p(4) and g(3)) or (p(7) and p(6) and p(5) and p(4) and p(3) and g(2))
		or (p(7) and p(6) and p(5) and p(4) and p(3) and p(2) and g(1)) or (p(7) and p(6) and p(5) and p(4)
		and p(3) and p(2) and p(1) and g(0)) or (p(7) and p(6) and p(5) and p(4) and p(3) and p(2) and p(1) 
		and p(0) and cin);
		
sum(0) <= p(0) xor cin;
sum(1) <= p(1) xor c1;
sum(2) <= p(2) xor c2;
sum(3) <= p(3) xor c3;
sum(4) <= p(4) xor c4;
sum(5) <= p(5) xor c5;
sum(6) <= p(6) xor c6;
sum(7) <= p(7) xor c7;

cout <= c8;
end Behavioral;

